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DATA SHEET
MOS INTEGRATED CIRCUIT
PD75P336
4-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The PD75P336 is a version of the PD75336 in which the on-chip mask ROM is replaced by one-time PROM. As the PD75P336 is user-programmable, it is suitable for preproduction in system development, and for short-run and multiple device-production. Detailed function description, etc. are described in the following User's manual. Be sure to read it when designing. PD75336 User's Manual: IEU-725
FEATURES * PD75336 compatible * Memory capacity:
* PROM : 16256 x 8 bits * RAM : 768 x 4 bits
* Operable over same supply voltage range as mask ROM PD75336
* VDD = 2.7 to 6.0 V
* On-chip 8-bits resolution A/D converter (successive approximation type) * On-chip LCD controller/driver ORDERING INFORMATION
Ordering Code Package 80-pin plastic QFP ( 14mm) 80-pin plastic TQFP (fine pitch)( 12mm) Quality Grade Standard Standard
PD75P336GC-3B9 PD75P336GK-BE9
5
Note
Pull-up resistor cannot be incorporated by mask option.
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The information in this document is subject to change without notice.
Document No. IC-2980A (O. D. No. IC-8371A) Date Published October 1993P Printed in Japan
The mark
5 shows major revised points.
(c) NEC Corporation 1993
2
BLOCK DIAGRAM
AN0-AN7*
8
AVREF AVSS
A/D CONVERTER PORT0 BASIC INTERVAL TIMER INTBT PROGRAM COUNTER (15) SP(8) CY ALU PORT 3 PORT 4 4 4 P30-P33 /MD0-MD3 P40-P43 4 P00-P03
PORT 1
4
P10-P13
PORT 2
4
P20-P23
TI0/P13 PTO0/P20
TIMER/EVENT COUNTER #0 INTT0 TIMER/EVENT COUNTER #1
TI1/P80 PTO1/P21
BANK
INTT1 WATCH TIMER GENERAL REG. PROGRAM MEMORY (ROM) 16256 x 8 BITS DECODE AND CONTROL
PORT 5
4
P50-P53
PORT 6
4
P60-P63
BUZ/P23
PORT 7 DATA MEMORY (RAM) 768 x 4 BITS
4
P70-P73
INTW SI/SB1/P03 SO/SB0/P02 SCK/P01
fLCD
CLOCKED SERIAL INTERFACE INTCSI
PORT 8
4
P80-P83
12 8 INTERRUPT CONTROL
8
S12-S23 S24/BP0 -S31/BP7 COM0-COM3 VLC0-VLC2 BIAS LCDCL/P30 SYNC/P31
INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0/P60 -KR3/P63 KR4/P70 -KR7/P73 fX / 2
N
SYSTEM CLOCK CLOCK CLOCK GENERATOR STAND BY OUTPUT DIVIDER SUB MAIN CONTROL CONTROL PCL/P22 * XT1 XT2 X1 X2 AN6/P82, AN7/P83
CPU CLOCK fLCD
LCD CONTROLLER /DRIVER
4 3
BIT SEQ. BUFFER (16)
PD75P336
VPP VDD VSS RESET
PD75P336
PIN CONFIGURATION (Top View) q 80-pin plastic QFP (s 14mm) s q 80-pin plastic TQFP (fine pitch) (s 12mm) s
P73/KR7 P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1 P60/KR0 RESET X2 AVREF AVSS AN5 AN4 AN3
5
X1 VPP* XT2
XT1
S31/BP7 S30/BP6 S29/BP5 S28/BP4 S27/BP3 S26/BP2 S25/BP1 S24/BP0 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12
1 2 3 4 5 6 7 8 9
8079787776 757473 7271 70696867666564636261
VDD
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
AN2 AN1 AN0 P83/AN7 P82/AN6 P81 P80/TI1 P33/MD3 P32/MD2 P31/SYNC/MD1 P30/LCDCL/MD0 P23/BUZ P22/PCL P21/PTO1 P20/PTO0 P13/TI0 P12/INT2 P11/INT1 P10/INT0 P03/SI/SB1
PD75P336GC-3B9 PD75P336GK-BE9
10 11 12 13 14 15 16 17 18
19 20 2122232425 262728 2930 31323334353637383940
P53 P00/INT4
*
In normal operation, VPP should be connected to VDD directly.
P01/SCK P02/SO/SB0
COM0
COM1 COM2
COM3 BIAS VLC0 VLC1 VLC2
P41 P42 P43 VSS
P40
P50
P51 P52
3
PD75P336
PIN NAME P00 to 03 P10 to 13 P20 to 23 P30 to 33 P40 to 43 P50 to 53 P60 to 63 P70 to 73 P80 to 83 BP0 to 7 KR0 to 7 AVREF AVSS AN0 to 7 SCK SI SO MD0 to 3 VPP : : : : : : : : : : : : : : : : : : : Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Bit Port Key Return Analog Reference Analog Ground Analog Input 0 to 7 Serial Clock Serial Input Serial Output Mode Selection Programming/Verifying Power Supply SB0, 1 RESET S12 to 31 COM0 to 3 VLC0 to 2 BIAS LCDCL SYNC TI0, 1 PTO0, 1 BUZ PCL INT0, 1, 4 INT2 X1, 2 XT1, 2 VDD VSS : : : : : : : : : : : : : : : : : : Serial Bus 0,1 Reset Input Segment Output 12 to 31 Common Output 0 to 3 LCD Power Supply 0 to 2 LCD Power Supply Bias Control LCD Clock LCD Synchronization Timer Input 0, 1 Programmable Timer Output 0, 1 Buzzer Clock Programmable Clock External Vectored Interrupt 0, 1, 4 External Test Interrupt 2 Main System Clock Oscillation 1, 2 Subsystem Clock Oscillation 1, 2 Positive Power Supply Ground
4
PD75P336
CONTENTS 1. PIN FUNCTIONS ......................................................................................................................................... 6
1.1 1.2 1.3 PORT PINS ............................................................................................................................................................. 6 OTHER PINS .......................................................................................................................................................... 8 PIN INPUT/OUTPUT CIRCUITS ...........................................................................................................................10
2. DIFFERENCES BETWEEN PD75P336 AND PD75336 ......................................................................... 13
2.1 2.2 PROGRAM MEMORY (PROM) 16256 WORDS x 8 BITS .................................................................................. 14 DATA MEMORY (RAM) 768 WORDS x 4 BITS .................................................................................................. 15
3. INSTRUCTION SET AND INSTRUCTION OPERATIONS ....................................................................... 16 4. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY OPERATIONS .................................. 25
4.1 4.2 4.3 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES ........................................................................... 26 PROGRAM MEMORY WRITE PROCEDURE ....................................................................................................... 27 PROGRAM MEMORY READ PROCEDURE ......................................................................................................... 28
5. ELECTRICAL SPECIFICATIONS ................................................................................................................ 29 6. PACKAGE INFORMATION ........................................................................................................................ 48 7. RECOMMENDED SOLDERING CONDITIONS ......................................................................................... 50 APPENDIX A. LIST OF FUNCTIONS.............................................................................................................. 51 APPENDIX B. DEVELOPMENT TOOLS ......................................................................................................... 52
5
PD75P336
1. PIN FUNCTIONS
1.1 PORT PINS (1/2)
Pin Name P00 P01 P02 P03 P10 P11
Input/Output Input Input/output Input/output Input/output
DualFunction Pin INT4 SCK SO/SB0 SI/SB1 INT0 INT1
Function
8-bit I/O
After Reset
I/O Circuit Type *1 B
4-bit input port (PORT0) Internal pull-up resistor specification by software is possible for P01 to P03 as a 3-bit unit.
x
F -A Input F -B M-C
With noise elimination circuit
Input P12 P13 P20 P21 Input/output P22 P23 P30 *2 P31 *2 Input/output P32 *2 P33 *2 MD2 MD3 PCL BUZ LCDCL MD0 SYNC MD1 INT2 TI0 PTO0 PTO1
4-bit input port (PORT1) Internal pull-up resistor specification by software is possible as a 4-bit unit.
x
Input
B -C
4-bit input/output port (PORT2) Internal pull-up resistor specification by software is possible as a 4-bit unit.
x
Input
E-B
Programmable 4-bit input/output port (PORT3) Input/output settable bit-wise. Internal pull-up resistor specification by software is possible as a 4-bit unit.
x
Input
E-B
P40 to P43 *2
Input/output
--
N-ch open-drain 4-bit input/output port (PORT 4). Data input/output pins for program memory (PROM) write/verify (low-order 4 bits). N-ch open-drain 4-bit input/output port (PORT 5) Data input/output pins for program memory (PROM) write/verify (high-order 4 bits).
Input
M-B
P50 to P53 *2
Input/output
--
Input
M-B
P60 P61 P62 P63 P70 P71 P72 P73 Input/output Input/output
KR0 KR1 KR2 KR3 KR4 KR5 KR6 KR7 4-bit input/output port (PORT7). Internal pull-up resistor specification by software is possible as a 4-bit unit. Programmable 4-bit input/output port (PORT6). Input/output settable bit-wise. Internal pull-up resistor specification by software is possible as a 4-bit unit.
Input
F -A
Input
F -A
* 1. 2.
: Indicates a Schmitt-triggered input. Direct LED drive capability.
6
PD75P336
1.1
PORT PINS (2/2)
Pin Name P80 P81
Input/Output
DualFunction Pin TI1 --
Function
8-bit I/O
After Reset
I/O Circuit Type E-E
Input/output P82 P83 BP0 BP1 Output BP2 BP3 BP4 BP5 Output BP6 BP7 S30 S31 S26 S27 S28 S29 AN6 AN7 S24 S25
4-bit input/output port (PORT8). Internal pull-up resistor specification by software is possible as a 4-bit unit.
x
E-B Input Y-B
1-bit output port (BIT PORT) Dual function as segment output pins.
x
*
G-C
*
VLCX shown below can be selected for the display outputs. S12 to S31: VLC1, COM0 to COM2: VLC2, COM3: VLC0 However, display output levels depend on the display outputs and VLCX external circuit.
7
PD75P336
1.2
OTHER PINS (1/2)
Pin Name TI0
Input/Output
DualFunction Pin P13
Function
After Reset
I/O Circuit Type * B -C
Input TI1 PTO0 output PTO1 PCL BUZ SCK SO/SB0 output output Input/output Input/output P21 P22 P23 P01 P02 P80 P20
External event pulse input pin for timer/event counter.
Input B -E
Timer/event counter output pin
Input
E-B
Clock output pin Frequency output pin (for buzzer or system clock trimming) Serial clock input/output pin Serial data output pin Serial bus input/output pin Serial data input pin Serial bus input/output pin Edge-detected vectored interrupt input pin (both rising and falling edge detection valid). Edge-detected vectored interrupt input pin (detected edge selectable) Edge-detected testable input pin (rising edge detection) Clocked
Input Input Input Input
E-B E-B F -A F -B
SI/SB1
Input/output
P03
Input
M-C B
INT4 INT0
Input
P00 P10
Input
Input INT1 INT2 KR0 to KR3 KR4 to KR7 Input Input Input P11 P12 P60 to P63 P70 to P73
Input Asynchronous Asynchronous Input Input Input
B -C
B -C F -A F -A
Parallel falling edge detected testable input pins. Parallel falling edge detected testable input pins. Main system clock oscillation crystal/ceramic resonator inputs. When an external clock is used, the clock is input to X1 and the inverted clock to X2. Subsystem clock oscillation crystal reasonator inputs When an external clock is used, the clock is input to XT1 and the inverted clock toXT2. XT1 can be used as a 1bit input (test) pin. System reset input pin. Mode selection pin for program memory (PROM) write/ verify. Program voltage application pin for program memory (PROM) write/verify. Applies +12.5 V in program memory write/verify. Directly connected to VDD in normal operation. Positive power supply pin GND potential pin
X1, X2
--
--
--
--
XT1, XT2
--
--
--
--
RESET MD0 to MD3
Input Input/output
-- P30 to P33
-- Input
B E-B
VPP
--
--
--
--
VDD VSS
-- --
-- --
-- --
-- --
*
: indicates a Schmitt-triggered input.
8
PD75P336
1.2
OTHER PINS (2/2)
Pin Name S12 to S23 S24 to S31 COM0 to COM3 VLC0 to VLC2 BIAS LCDCL*1 SYNC *1 AN0 to AN5 AN6 AN7 AVREF AVSS
Input/Output Output Output Output Input Output Output Output
DualFunction Pin -- BP0 to 7 -- -- -- P30 P31 --
Function Segment signal output pins Segment signal output pins Common signal output pins LCD drive power supply pins External split cutting output pin External extension driver drive clock output pin External extension driver synchronization drive clock output pin
After Reset *2 *2 *2 -- High impedance
I/O Circuit Type G-A G-C G-B --
-- Input Input E-B E-B Y A/D converter analog signal input pins Input Y -B P83 Input -- -- -- A/D converter reference voltage input pin A/D converter GND potential pin -- -- Z Z
Input
P82
* 1. 2.
Pins provided for future system expansion. Currently used only as pins 30 and 31. VLCX shown below can be selected for the display outputs. S12 to S31: VLC1, COM0 to COM2: VLC2, COM3:VLC0 However, display output levels depend on the display outputs and VLCX external circuit.
9
PD75P336
1.3 PIN INPUT/OUTPUT CIRCUITS The input/output circuits for each of the pin PD75P336 are shown below in partially simplified form. TYPE A (For TYPE E-B)
VDD data P-ch IN N-ch output disable N-ch P-ch OUT
TYPE D (For TYPE E-B, F-A)
VDD
CMOS Standard Input Buffer TYPE B
Push-Pull Output that can be Made High-Impedance Output (P-ch and N-ch OFF) TYPE E-B
VDD P.U.R. output disable P-ch
IN
data Type D output disable
IN/OUT
Type A
P.U.R.:Pull-Up Resistor
Schmitt-Trigger Input with Hysteresis Characteristic
TYPE B-C
TYPE E-E
VDD P.U.R.
VDD P.U.R. P.U.R. enable
P.U.R. enable data output disable Type D
P-ch
IN/OUT
P-ch
Type A
IN
Type B
P.U.R. : Pull-Up Resistor
Schmitt-Trigger Input with Hysteresis Characteristic
P.U.R.:Pull-Up Resistor
10
PD75P336
TYPE F-A
VDD P.U.R. P.U.R. enable data Type D output disable P-ch
TYPE G-B
VLC0 VLC1 P-ch N-ch
IN/OUT
P-ch
OUT COM data N-ch
Type B
P-ch
VLC2 N-ch
P.U.R.:Pull-Up Resistor
TYPE F-B
VDD P.U.R. P.U.R. enable P-ch VDD P-ch
TYPE G-C
VDD P-ch VLC0 VLC1 P-ch SEG data/Bit Port data VLC2 N-ch OUT N-ch
output disable (P) data output disable output disable (N)
IN/OUT
N-ch
P.U.R.:Pull-Up Resistor
TYPE G-A
TYPE M-B
VLC0 P-ch VLC1 P-ch SEG data N-ch VLC2 N-ch
Middle-High Voltage Input Buffer data output disable N-ch
IN/OUT
OUT
11
PD75P336
TYPE M-C
VDD P.U.R. P.U.R. enable P-ch IN/OUT
TYPE Y-B
VDD
P.U.R enable data output disable Type D
P-ch
IN/OUT
data output disable
N-ch
Type A
Type Y P.U.R.:Pull-Up Resistor P.U.R:Pull-Up Resistor
TYPE Y
TYPE Z
VDD IN VDD P-ch N-ch
+
IN
Sampling C
-
AVSS
AVSS Reference Voltage (From Series Resistance Voltage Tap)
Reference Voltage
input enable
AVSS
12
PD75P336
2. DIFFERENCES BETWEEN PD75P336 AND PD75336
Parameter Program memory Data memory Ports 4, 5 pull-up resistor LCD drive power supply split resistor Subsystem clock oscillation feedback resistor Pin 69
PD75336
Mask ROM 16256 x 8 bits 768 x 4 bits Incorporation specifiable by mask option Incorporation specifiable by mask option Incorporation specifiable by mask option IC
PD75P336
One-time PROM 16256 x 8 bits 768 x 4 bits No
No
Incorporated VPP
13
PD75P336
2.1 PROGRAM MEMORY (PROM) ..... 16256 WORDS x 8 BITS The program memory consists of 16256-byte PROM. The program memory map is shown in Fig. 2-1. Fig. 2-1 Program Memory Map
7 0000H MBE 6 RBE 0 Internal Reset Start Address (High-Order 6 Bits) (Low-Order 8 Bits) 0002H MBE RBE
INTBT/INT4 Start Address
(High-Order 6 Bits) (Low-Order 8 Bits)
0004H
MBE
RBE
INT0 Start Address
(High-Order 6 Bits) (Low-Order 8 Bits) CALLF !faddr Instruction Entry Address BRCB !caddr Instruction Branch Address BR !addr Instruction Branch Address CALL !addr Instruction Branch Address
0006H
MBE
RBE
INT1 Start Address
(High-Order 6 Bits) (Low-Order 8 Bits)
0008H
MBE
RBE
INTCSI Start Address
(High-Order 6 Bits) (Low-Order 8 Bits)
000AH
MBE
RBE
INTT0 Start Address
(High-Order 6 Bits) (Low-Order 8 Bits)
000CH
MBE
RBE
INTT1 Start Address
(High-Order 6 Bits) (Low-Order 8 Bits)
0020H GETI Instruction Reference Table
Branch/Call Address, by GETI BR $addr Instruction Relative Branch Address (-15 to -1, +2 to +16)
007FH 0080H
07FFH 0800H

0FFFH 1000H BRCB !caddr Instruction Branch Address
1FFFH 2000H
2FFFH 3000H
BRCB !caddr Instruction Branch Address
3F7FH
BRCB !caddr Instruction Branch Address
14
PD75P336
Remarks
In addition to the above, branching is possible with the BR PCDE and BR PCXA instructions to addresses with the low-order 8 bits only of the PC modified.
2.2
DATA MEMORY (RAM) .......768 WORDS x 4 BITS
The configuration of the data memory is shown in Fig. 2-2. The data memory comprises a data area and peripheral hardware area, the data area comprises 768 x 4-bit static RAM.
Fig. 2-2 Data Memory Map
Data Memory General Register Area Stack Area 000H 01FH 020H (32 x 4)
Memory Bank 0 0FFH 100H 256 x 4
Data Area Static RAM 768 x 4 Display Data Memory Area
Memory Bank 1 1EBH 1ECH 1FFH 200H 256 x 4 (20 x 4)
Memory Bank 2 2FFH Not On-Chip 256 x 4
F80H Peripheral Hardware Area FFFH Memory Bank 15 128 x 4
15
PD75P336
3. INSTRUCTION SET AND INSTRUCTION OPERATIONS
(1) Operand identifier and description Operand identifiers and description method operands are written in the operand column for each instruction in accordance with the description method for the operand identifier for that instruction (refer to "RA75X Assembler Package User's Manual Language Volume (EEU-730)" for details). Where multiple items are included in the description method, one of those elements should be selected. Uppercase letters and the symbols + and - are keywords and should be written as they are. In the case of immediate data, an appropriate number or label is written.
Descriptor reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr caddr faddr taddr PORTn IExxx RBn MBn *
Description Method X, A, B, C, D, E, H, L X, B, C, D, E, H, L XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE' HL' BC, DE, HL, XA', BC', DE', HL' HL, HL+, HL-, DE, DL DE, DL 4-bit immediate date or label 8-bit immediate date or label 8-bit immediate date or label* 2-bit immediate date or label FB0H to FBFH, FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label 0000H to 3F7FH immediate data or label 12-bit immediate date or label 11-bit immediate date or label 20H to 7FH immediate date (bit 0 = 0) or label PORT0 to PORT8 IEBT, IECSI, IET0, IET1, IE0 to IE2, IE4, IEW RB0 to RB3 MB0, MB1, MB2, MB15
In 8-bit data processing, only an even address can be specified.
16
PD75P336
(2) Operation description legend A : A register; 4-bit accumulator B : B register; 4-bit accumulator C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE PORTn IME IPS IExxx RBS MBS PCC . (xx) xxH : : : : : : : : : : : : : : : : : : : : : : : : : : : : C register; 4-bit accumulator D register; 4-bit accumulator E register; 4-bit accumulator H register; 4-bit accumulator L register; 4-bit accumulator X register; 4-bit accumulator Register pair (XA); 8-bit accumulator Register pair (BC); 8-bit accumulator Register pair (DE); 8-bit accumulator Register pair (HL); 8-bit accumulator Extended register pair (XA') Extended register pair (BC') Extended register pair (DE') Extended register pair (HL') Program counter Stack pointer Carry flag; bit accumulator Program status word Memory bank enable flag Register bank enable flag Portn (n = 0 to 8) Interrupt master enable flag Interrupt priority selection register Interrupt enable flag Register bank selection register Memory bank selection register Processor clock control register Address, bit delimiter
: Contents addressed by xx : Hexadecimal data
17
PD75P336
(3) Description of addressing area field symbols
*1 *2
MB = MBE * MBS MB = 0
MBS = 0, 1, 2, 15
*3
MBE = 0 : MB = 0 (000H to 07FH) MB = 15 (F80H to FFFH) MBE = 1 : MB = MBS (MBS = 0, 1, 2, 15) MB = 15, fmem = FB0H to FBFH, FF0H to FFFH MB = 15, pmem = FC0H to FFFH addr = 0000H to 3F7FH addr = (Current PC) -15 to (Current PC) -1 (Current PC) + 2 to (Current PC) + 16 caddr = 0000H to 0FFFH (PC13,12 = 00B) or 1000H to 1FFFH (PC13,12 = 01B) or 2000H to 2FFFH (PC13,12 = 10B) or 3000H to 3FFFH (PC13,12 = 11B) faddr = 0000H to 07FFH taddr = 0020H to 007FH
Data Memory Addressing
*4 *5 *6 *7
*8
Program Memory Addressing
*9 *10
Remarks
1. 2. 3. 4.
MB indicates the accessible memory bank. MB=0 irrespective of MBE and MBS in *2. MB=15 irrespective of MBE and MBS in *4 and *5. *6 to *10 indicate accessible area.
(4) Explanation of machine cycle column "S" indicates the number of machine cycles required when an instruction with a skip function performs a skip operation. The value of "s" is as follows: * When a skip is not performed ....................................................................................................................... S = 0 * When the skipped instruction is a 1-byte or 2-byte instruction ................................................................ S = 1 * When the skipped instruction is a 3-byte instruction (BR !addr or CALL !addr) ................................... S = 2 Note A GETI instruction is skipped in one machine cycle. any of four times can be
One machine cycle is equivalent to one cycle (=tCY)of the CPU clock cycle : selected according to the PCC setting.
18
PD75P336
Mnemonic
Machine Cycles
Note 1
Bytes
Operand
Operation A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) A (HL), then L L + 1 A (HL), then L L - 1 A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg XA rp' reg1 A rp'1 XA A (HL) A (HL), then L L + 1 A (HL), then L L -1 A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp' XA (PC13-8 + DE)ROM XA (PC13-8 + XA)ROM
Addressing Area
Skip Condition Stack A
A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL- A, @rpa1 XA, @HL MOV @HL, A Transfer @HL, XA A, mem XA, mem mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA A, @HL A, @HL+ A, @HL- A, @rpa1 XCH XA, @HL A, mem XA, mem A,reg1 XA, rp' Note 2 XA, @PCDE MOVT XA, @PCXA
1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1
1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 3 3
Stack A Stack B
*1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH
*1 *1 *1 *2 *1 *3 *3 L=0 L = FH
Note 1. 2.
Instruction Group Table reference
19
PD75P336
Mnemonic
Machine Cycles
Note
Bytes
Operand CY, fmem.bit
Operation CY (fmem.bit) CY (pmem7-2 + L3-2.bit (L1-0)) CY (H + mem3-0.bit) (fmem.bit) CY (pmem7-2 + L3-2.bit (L1-0)) CY (H + mem3-0.bit) CY A A + n4 XA XA + n8 A A + (HL) XA XA + rp' rp'1 rp'1 + XA A, CY A + (HL) + CY XA, CY XA + rp' + CY rp'1, CY rp'1 + XA + CY A A - (HL) XA XA - rp' rp'1 rp'1 - XA A , CY A - (HL) - CY XA, CY XA - rp' - CY rp'1, CY rp'1 - XA - CY AA AA
Addressing Area *4 *5 *1 *4 *5 *1
Skip Condition
2 2 2 2 2
2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2
Bit transfer
CY, pmem.@L MOV1 CY, @H + mem.bit fmem.bit, CY pmem.@L, CY
@H + mem.bit, CY 2 A, #n4 XA, #n8 ADDS A, @HL XA, rp' rp'1, XA A, @HL ADDC XA, rp' rp'1, XA A, @HL SUBS Operation XA, rp' rp'1, XA A, @HL SBUC XA, rp' rp'1, XA A, #n4 AND A, @HL XA, rp' rp'1, XA A, #n4 OR A, @HL XA, rp' rp'1, XA A, #n4 XOR A, @HL XA, rp' rp'1, XA 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2
carry carry *1 carry carry carry *1
*1
borrow borrow borrow
*1
n4 (HL) rp' XA
*1 *1
XA XA
rp'1 rp'1 AA AA
n4 (HL) rp' XA
*1
XA XA
rp'1 rp'1 AA AA
n4 (HL) rp' XA
XA XA
rp'1 rp'1
Note Instruction Group
20
PD75P336
Mnemonic RORC NOT A A reg INCS rp1
Machine Cycles
Note 1
Bytes
Operand
Operation CY A0, A3 CY, An-1 An AA reg reg + 1 rp1 rp1 + 1 (HL) (HL) + 1 (mem) (mem) + 1 reg reg - 1 rp' rp' - 1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY 1 CY 0 Skip if CY = 1 CY CY
Addressing Area
Skip Condition
Note 2
1 2 1 1 2 2 1 2 2 2 1 2 2 2 1 1 1 1
1 2 1+S 1+S 2+S 2+S 1+S 2+S 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1
reg = 0 rp1 = 00H *1 *3 (HL) = 0 (mem) = 0 reg = FH rp' = FFH reg = n4 *1 *1 *1 (HL) = n4 A = (HL) XA = (HL) A = reg XA = rp'
Note 3
@HL mem reg DECS rp' reg, #n4
Comparison
@HL, #n4 SKE A, @HL XA, @HL A, reg XA, rp' SET1 CY CY CY CY
Note 4
CLR1 SKT NOT1
CY = 1
Note 1. 2. 3. 4.
Instruction Group Accumulator operation Increment and decrement Carry flag manipulation
21
PD75P336
Machine Cycles
Bytes
Note
Mnemonic
Operand
Operation
Addressing Area *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1
Skip Condition
mem.bit SET1 fmem.bit pmem.@L @H + mem.bit mem.bit CLR1 fmem.bit pmem.@L @H + mem.bit mem.bit SKT Memory bit manipulation fmem.bit pmem.@L @H + mem.bit mem.bit SKF fmem.bit pmem.@L @H + mem.bit fmem.bit SKTCLR pmem.@L @H+mem.bit CY, fmem.bit AND1 CY, pmem.@L
CY, @H + mem.bit
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2
(mem.bit) 1 (fmem.bit) 1 (pmem7-2 + L3-2.bit (L1-0)) 1 (H + mem3-0.bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem7-2 + L3-2.bit (L1-0)) 0 (H + mem3-0.bit) 0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1 Skip if (pmem7-2 + L3-2.bit (L1-0)) = 1 Skip if (H + mem3-0.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (pmem7-2 + L3-2.bit (L1-0))= 0 Skip if (H + mem3-0.bit) = 0 Skip if (fmem.bit) = 1 and clear Skip if (pmem7-2 + L3-2.bit (L1-0)) = 1 and clear Skip if (H + mem3-0.bit) = 1 and clear CY CY CY CY CY CY CY CY CY CY CY CY CY CY CY CY CY CY
(mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1
(@H + mem.bit) = 1
(mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0
(@H + mem.bit) = 0
(fmem.bit) = 1 (pmem.@L) = 1
(@H + mem.bit) = 1
(fmem.bit) (pmem7-2 + L3-2.bit (L1-0)) (H + mem3-0.bit) (fmem.bit) (pmem7-2 + L3-2.bit (L1-0)) (H + mem3-0.bit) (fmem.bit) (pmem7-2 + L3-2.bit (L1-0)) (H + mem3-0.bit)
CY, fmem.bit OR1 CY, pmem.@L
CY, @H + mem.bit
CY, fmem.bit XOR1 CY, pmem.@L
CY, @H + mem.bit
BR
addr
--
--
PC13-0 addr (The assembler selects the optimum instruction from among the BRCB !caddr, and BR $addr instructions.) PC13-0 addr PC13-0 PC
13.12
*6
Branch
BR BRCB BR BR
!addr !caddr $addr PCDE PCXA
3 2 1 2 2
3 2 2 3 3
*6 + caddr11-0 *8 *7 + DE + XA
PC13-0 addr PC13-0 PC PC13-0 PC
13-8 13-8
Note
Instruction Group
22
PD75P336
Machine Cycles
Note 1
Bytes
Mnemonic
Operand
Operation
Addressing Area
Skip Condition
CALL
!addr
3
3
(SP - 4) (SP - 1) (SP - 2) PC11-0 (SP - 3) MBE, RBE, PC13.12 PC13-0 addr, SP SP - 4 (SP - 4) (SP - 1) (SP - 2) PC11-0 (SP - 3) MBE, RBE, PC13.12 PC13-0 000 + faddr, SP SP - 4 MBE, RBE, PC13.12 (SP + 1) PC11-0 (SP) (SP + 3) (SP + 2) SP SP + 4 MBE, RBE, PC13.12 (SP + 1) PC11-0 (SP) (SP + 3) (SP + 2) SP SP + 4 the skip unconditionally x, x, PC13.12 (SP + 1) PC11-0 (SP) (SP + 3) (SP + 2) PSW (SP + 4) (SP + 5), SP SP + 6 (SP - 1) (SP - 2) rp, SP SP - 2 (SP - 1) MBS, (SP - 2) RBS, SP SP - 2 rp (SP + 1) (SP), SP SP + 2 MBS (SP + 1), RBS (SP), SP SP + 2 IME (IPS.3) 1 IE x x x 1 IME (IPS.3) 0 IE x x x 0 A PORTn (n = 0-8) (n = 4, 6) (n = 2-8) (n =4, 6)
*6
CALLF
!faddr
2
2
*9
Subroutine stack control
RET
1
3
RETS
1
3+S
Unconditional
RETI
1
3
PUSH
rp BS
1 2 1 2 2
1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2
POP
rp BS
EI Note 2
IEx x x
2 2
DI
IEx x x A, PORTn XA, PORTn
2 2 2 2 2 2 2 1
Input/Output
IN*1
XA PORTn+1, PORTn PORTn A PORTn+1, PORTn XA Set HALT Mode (PCC.2 1) Set STOP Mode (PCC.3 1) No Operation RBS n MBS n
OUT*1 HALT STOP NOP SEL
PORTn, A PORTn, XA
*10
Note 3
RBn MBn
2 2
(n = 0-3) (n = 0,1,2,15)
GETI*2
taddr
1
3
* TBR Instruction PC13-0 (taddr) 5-0 + (taddr + 1) ----------------------------------------------------------------------* TCALL Instruction (SP - 4) (SP - 1) (SP - 2) PC11-0 (SP - 3) MBE, RBE, PC13, 12 PC13-0 (taddr) 5-0 (taddr + 1) SP SP - 4 ----------------------------------------------------------------------* Other than TBR and TCALL Instruction Execution of an instruction addressed at (taddr) and (taddr + 1)
-----------------------------
Special
----------------------------Conforms to referenced instruction.
23
PD75P336
* 1. At IN/OUT instruction execution, MBE = 0 or MBE = 1, MBS = 15 must be set in advance. 2. TBR and TCALL instructions are assembler pseudo-instructions for table definition.
Note 1. Instruction Group 2. Interruput control 3. CPU control
24
PD75P336
4. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY OPERATIONS
The program memory incorporated in the PD75P336 is 32640 x 8-bit electrically writable one-time PROM. Write/verify operations on this one-time PROM are executed using the pins shown in the table below. Address updating is performed by means of clock input from the X1 pin rather than by address input.
Pin Name VPP
Function Voltage applecation pin for program memory write/verify (normally VDD potential). Address update clock inputs for program memory write/verify. Inverse of X1 pin signal is input to X2 pin. Operating mode selection pin for program memory write/verify. 8-bit data input/output pins for progrm memory write/verify. Supply voltage application pin. Applies 2.7 to 6.0 V in normal operation, and 6 V for program memory write/verify.
X1, X2 MD0 to MD3 P40 to P43 (low-order 4 bits) P50 to P53 (high-order 4 bits)
VDD
Note
1. Pins not used in a program memory write/verify operation are handled as follows: * Pins other than XT2 .......... Connect to VSS with a pull-down resistor * XT2 pins ............................. Leave open 2. Since the PD75P336 is not provided with an erase window, program memory contents cannot be erased with ultra-violet light.
4.1 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES When +6 V is applied to the VDD pin and +12.5 V to the VPP pin, the PD75P336 enters the program memory write/ verify mode. This mode comprises one of the operating modes shown below according to the setting of pins MD0 to MD3.
Operating Mode Setting Operating Mode VPP VDD MD0 H L +12.5 V +6V L H L X H H H H Verify mode Program inhibit mode MD1 L H MD2 H H MD3 L H Program memory address zero-clear Write mode
X: L or H
25
PD75P336
4.2 PROGRAM MEMORY WRITE PROCEDURE The procedure for writing to program memory is as shown below, allowing high-speed writing. (1) Unused pins are connected to VSS with a pull-down resistor. The X1 pin is driven low. (2) 5 V is supplied to the VDD and VPP pins. (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) 10 s wait. Program memory address zero-clear mode. 6 V is supplied to VDD, 12.5 V to VPP. Program inhibit mode. Data is written in 1 ms write mode. Program inhibit mode. Verify mode. If write is successful go to (10), otherwise repeat (7) to (9). (Number of times written in (7) to (9): X) x 1 ms additional writes. Program inhibit mode. Program memory address is updated (+1) by inputting 4 pulses to the X1 pin. Steps (7) to (12) are repeated until the last address. Program memory address zero-clear mode.
(15) VDD / VPP pin voltage is changed to 5 V. (16) Power-off. Steps (2) to (12) of this procedure are shown in the figure below.
Repeated X Times
Write
Verify
Additional Write
Address Increment
VPP VPP VDD VDD + 1 VDD VDD X1 P40-P43 P50-P53
Data Input
Data Output
Data Input
MD0 (P30) MD1 (P31) MD2 (P32) MD3 (P33)

26
PD75P336
4.3 PROGRAM MEMORY READ PROCEDURE PD75P336 program memory contents can be read using the following procedure. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) Unused pins are connected to VSS with a pull-down resistor. The X1 pin is driven low. 5 V is supplied to the VDD and VPP pins. 10 s wait. Program memory address zero-clear mode. 6 V supplied to VDD, and 12.5 V to VPP. Program inhibit mode. Verify mode. When clock pulses are input to the X1 pin, data is output sequentially, one address per 4-pulse-input cycle. Program inhibit mode. Program memory address zero-clear mode. VDD / VPP pin voltage is changed to 5 V. Power-off.
Steps (2) to (9) of this procedure are shown in the figure below.
VPP VPP VDD
VDD + 1 VDD VDD
X1
MD0 (P30)
MD1 (P31)
MD2 (P32)
MD3 (P33)

P40-P43 P50-P53
Data Output
Data Output

27
PD75P336 PD75P336 PD75304B
5. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25 C)
PARAMETER SYMBOL VDD Power supply voltage VPP VI1 VI2 Output voltage Output current high VO IOH 1 pin All pins 1 pin Output current low Peak value Effective value Peak value IOL* Total of ports 0, 2, 3, 5, 18 Effective value Peak value Effective value Except ports 4, 5 Ports 4, 5 Open-drain TEST CONDITIONS RATING -0.3 to +7.0 -0.3 to +13.5 -0.3 to VDD +0.3 -0.3 to +11 -0.3 to VDD +0.3 -15 -30 30 15 100 60 100 60 -40 to +85 -65 to +150 UNIT V V V V V mA mA mA mA mA mA mA mA C C
5
Input voltage
Total of ports 4, 6, 7 Operating temperature Storage temperature Topt Tstg
*
Rms value is calculated from [effective value] = [peak value] x duty
CAPACITANCE (Ta = 25 C, VDD = 0 V)
PARAMETER Input capacitance Output capacitance I/O capacitance SYMBOL CIN COUT CIO f = 1 MHz Unmeasured pins returned to 0 V. TEST CONDITIONS MIN. TYP. MAX. 15 15 15 UNIT pF pF pF
28
PD75P336 PD75P336 PD75304B
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
ESONATOR
RECOMMENDED CONSTANT
PARAMETER Oscillator frequency (fx)*1
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
1.0 After VDD reached the MIN. of the oscillator voltage range. 1.0 VDD = 4.5 to 6.0 V 4.19
5.0*3
MHz
X1
X1
Ceramic resonator
C1 C2
Oscillation stabilization time*2
4
ms
VDD
X1
X1
Oscillator frequency (fx)*1
5.0*3
MHz
Crystal resonator
C1 C2
Oscillation stabilization time*2
10
ms
30
ms
VDD
X1
X2
X1 input frequency (fx)*1
1.0
5.0*3
MHz
External clock
PD74HCU04
X1 input high-/low-level width (tXH, tXL)
100
500
ns
*
1. Shows the oscillator characteristics only. For the instruction execution time, see the AC characteristics. 2. Time necessary for oscillation to stabilize after VDD applied or STOP mode released. 3. When the oscillator frequency is "4.19 MHz < fX 5.0 MHz", it is impossible to select of "PCC = 0011" with 1 machine cycle of less than 0.95 s as instruction execution time.
29
PD75P336 PD75P336 PD75304B
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
RECOMMENDED CONSTANT TEST CONDITIONS
RESONATOR
PARAMETER
MIN.
TYP.
MAX.
UNIT
XT1
XT2 R
Oscillator frequency (fXT) VDD = 4.5 to 6.0 V Oscillation stabilization time
32
32.768
35
kHz
Crystal resonator
C3
1.0
2
s
C4
10
s
VDD
XT1 input frequency (fXT)
XT1 XT2 Leave Open
32
100
kHz
External clock
XT1 input high-/ low-level width (tXTH,tXTL) 5 15
s
Note
When the main system clock and subsystem clock oscillation circuit are used, area inside doted lines in the figure should be wired as follows to prevent influence from the wiring capacitance, etc.. * Wiring should be as short as possible. * Do not cross other signal lines, and do not place the oscillator close to line in which varying high current flows. * Potential at the oscillator capacitor connecting point should always be the same as VDD. Do not connect to the power supply pattern in which high current flows. * Do not fetch signals from the oscillator. In the subsystem clock oscillator, which is designed to be a circuit with low amplification ratio to suppress consumption current, misoperation due to noise occurs more often than in the main system clock oscillator. Therefore, when using the subsystem clock, special care should be taken in the wiring method.
30
PD75P336 PD75P336 PD75304B
DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) (1/3)
PARAMETER SYMBOL VIH1 Input voltage high VIH2 VIH3 VIH4 VIL1 Input voltage low VIL2 VIL3 TEST CONDITIONS Ports 2, 3, 8 Ports 0, 1, 6, 7, RESET Ports 4 and 5 X1, X2, XT1 Ports 2, 3, 4, 5, 8 Ports 0, 1, 6, 7 RESET X1, X2, XT1 VDD = 4.5 to 6.0 V IOH = -1 mA IOH = -100 A VDD = 4.5 to 6.0 V IOH = -100 A IOH = -50 A Open-drain MIN. 0.7 VDD 0.8 VDD 0.7 VDD VDD -0.5 0 0 0 TYP. MAX. VDD VDD 10 VDD 0.3 VDD 0.2 VDD 0.4 UNIT V V V V V V V
VOH1 Output voltage high VOH2
Ports 0, 2, 3, 6, 7, 8 BIAS
VDD -1.0
V
VDD -0.5
V
BP0 to BP7 (IOH 2 outputs)
VDD -2.0
V
VDD -1.0
V
31
PD75P336 PD75P336 PD75304B
DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) (2/3)
PARAMETER
SYMBOL
TEST CONDITIONS Ports 3, 4, 5 VDD = 4.5 to 6.0 V IOL = 15 mA Ports 0, 2, 3, 4, 5, 6 7, 8 VDD = 4.5 to 6.0 V IOL = 1.6 mA IOL = 400 A Open-drain pull-up
MIN.
TYP.
MAX.
UNIT
0.4
2.0
V
VOL1 Output voltage low
0.4
V
0.5
V
SB0, 1 resistor 1 k
0.2 VDD
V
VOL2
BP0 to BP7 (IOL 2 outputs)
VDD = 4.5 to 6.0 V IOL = 100 A IOL = 50 A Other than below
1.0
V
1.0 3 20
V
ILIH1 VIN = VDD Input leakage current high ILIH2 VIN = 10 V
A A A
X1, X2, XT1 Ports 4, 5 (when opendrain) Other than below VIN = 0 V X1, X2, XT1 Other than below Ports 4 and 5 (when opendrain)
ILIH3
20
Input leakage current low
ILIL1 ILIL2 ILOH1 VOUT = VDD
-3 -20 3
A A A
Output leakage current high
ILOH2
VOUT = 10 V
20
A
Output leakage current low
ILOL
VOUT = 0 V VDD = 5.0 V 10% VDD = 3.0 V 10%
-3
A
Built-in Pull-up resistor
RL1
Ports 0, 1, 2, 3, 6 7, 8 (Except P00) VIN = 0 V
15
40
80
k
30
300
k
LCD drive voltage
VLCD
2.5
VDD
V
32
PD75P336 PD75P336 PD75304B
DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) (3/3)
PARAMETER LCD output voltage deviation*1 (common) LCD output voltage deviation*1 (segment) SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
VODC
IO = 5 A
VODS
IO = 1 A
VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 2.7 V VLCD VDD
0
0.2V
V
0
0.2V
V
VDD = 5 V 10 %*4 IDD1 4.19 MHz crystal oscillation C1= C2 = 22 pF*3 IDD2 VDD = 3 V 10 %*5 VDD = 5V 10 % VDD = 3V 10 %
5
15
mA
1
3
mA
500
1500
A
HALT mode
300
900
Power supply current *2 IDD3 32 kHz crystal oscillation*6
A
Operat- VDD = 3V ing 10 % mode HALT mode VDD = 3V 10 %
100
300
A
IDD4
20
60
A
VDD = 5 V 10 % XT1 = 0 V STOP mode IDD5 VDD = 3V 10 % Ta = 25 C
0.5
20
A
0.1
10
A A
0.1
5
*
1. The voltage deviation means a difference between the ideal value of segment or common output (VLCDn; n = 0, 1, 2) and the output voltage. 2. Current flowing in the built-in pull-up resistor and the LCD split resistor is not include. 3. Including the case where the subsystem clock is operating. 4. When the processor clock control register (PCC) is set to 0011 and operated in high-speed mode. 5. When PCC is set to 0000 and operated in the low-speed mode. 6. The case where the system clock control register (SCC) is set to 1001, the main system clock oscillatio stopped and the device is operated on the subsystem clock.
33
PD75P336 PD75P336 PD75304B
A/D CONVERTER CHARACTERISTICS
PARAMETER Resolution -10 Ta + 85 oC -40 Ta < -10 oC -10 Ta + 85 oC SYMBOL
(Ta = -40 to +85 C, VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V)
TEST CONDITION MIN. 8 TYP. 8 MAX. 8 1.5 UNIT bit
2.5 V AVREF VDD AVREF 0.6 VDD
2.0
Absolute accuracy*1
2.5 V AVREF VDD AVREF < 0.6 VDD
tCY 1.91 s -40 Ta - 10 oC
1.5
LSB
2.0
-40 tCY < 1.91 s Ta + 85 oC Conversion time Sampling time Analog input voltage Analog input impedance AVREF current tCONV tSAMP VIAN *2 *3 AVSS
3.0 168/fx 44x AVREF
s s
V
RAN IREF
1000 1.0 2.0
M mA
*
1. Absolute accuracy excluding quantization (1/2LSB) error. 2. Time up to end of conversion (EOC = 1) after execution of the conversion start instruction. (40.1 s: fx = 4.19 MHz operation) 3. Time up to end of sampling after execution of the conversion start instruction. (10.5 s: fx = 4.19 MHz operation)
34
PD75P336 PD75P336 PD75304B
AC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V)
PARAMETER SYMBOL TEST CONDITIONS Operated by main system clock Operated by subsystem clock fTI VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. 0.95 TYP. MAX. 64 UNIT
s s s
CPU clock cycle time (minimum instruction execution time = 1 machine cycle)*1
tCY
3.8
64
114
122
125
TI0, 1 input frequency
0 0
1 275
MHz kHz
TI0, 1 input high/ low level width
tTIH, tTIL
VDD = 4.5 to 6.0 V
0.48 1.8
s s s s s s
INT0 Interrupt input high/ low level width tINTH, INT1, 2, 4 tINTL KR0 to KR7 RESET low level width tRSL
*2 10 10 10
* 1.
The CPU clock () cycle time is determined by the oscillator frequency of the connected resonator and the system clock control register (SCC) and the processor clock control register (PCC). The figure below shows the main system clock operation power supply voltage VDD vs cycle time tCY characteristics. Becomes 2tCY or 128/fX depending on the interrupt mode register (IM0) setting.
70 64 30 6 5 4
tcy vs VDD (Operating on Main System Clock)
Operating Guaranteed Range
2.
Cycle Time tcy [ s]
3
2
1
0.5 0 1 2 3 4 5 6
Supply Voltage VDD [V]
35
PD75P336 PD75P336 PD75304B
SERIAL TRANSFER OPERATION 2-wired and 3-wired serial I/O modes (SCK ... Internal clock output)
PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY1 3800 VDD = 4.5 to 6.0 V tKCY1 /2-50 tKCY1 /2-150 150 ns ns MIN. 1600 TYP. MAX. UNIT ns
tKL1 SCK high/low level width tKH1
ns
SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK
tSIK1
ns
tKSI1 VDD = 4.5 to 6.0 V
400
ns
tKSO1
RL = 1 k , CL = 100 pF*
250 1000
ns ns
2-wired and 3-wired serial I/O modes (SCK ... External clock input)
PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY2 3200 SCK high/low level width SI setup time (to SCK) SI hold time (from SCK ) SO output delay time from SCK tKL2 tKH2 tSIK2 VDD = 4.5 to 6.0 V 400 1600 100 ns ns ns ns MIN. 800 TYP. MAX. UNIT ns
tKSI2 VDD = 4.5 to 6.0 V
400 300 1000
ns ns ns
tKSO2
RL = 1 k, CL = 100 pF*
*
RL and CL are the SO output line load resistance and load capacitance, respectively.
36
PD75P336 PD75P336 PD75304B
SBI mode (SCK ... Internal clock output (master))
PARAMETER SYMBOL UNIT ns ns ns
TEST CONDITIONS VDD = 4.5 to 6.0 V
MIN. 1600 3800
TYP.
MAX.
SCK cycle time
tKCY3
tKL3 SCK high/low level width tKH3
VDD = 4.5 to 6.0 V
tKCY3 /2-50 tKCY3 /2-150 150
ns
SB0,1 setup time (to SCK) SB0,1 hold time (from SCK) SB0,1 output delay time from SCK SB0,1 from SCK
tSIK3
ns
tKSI3
tKCY3/2 VDD = 4.5 to 6.0 V
ns
tKSO3
RL = 1 k , CL = 100 pF*
0 0
250 1000
ns ns
tKSB
tKCY3
ns
SCK from SB0, 1
tSBK
tKCY3
ns
SB0,1 low level width SB0,1 high level width
tSBL
tKCY3
ns
tSBH
tKCY3
ns
*
RL and CL are the SB0 and SB1 output line load resistance and load capacitance, respectively.
37
PD75P336 PD75P336 PD75304B
SBI mode (SCK ... External clock input (slave))
PARAMETER SYMBOL UNIT ns ns ns
TEST CONDITIONS VDD = 4.5 to 6.0 V
MIN. 800 3200
TYP.
MAX.
SCK cycle time
tKCY4
tKL4 SCK high/low level width tKH4
VDD = 4.5 to 6.0 V
400
1600
ns
SB0,1 setup time (to SCK) SB0,1 hold time (from SCK) SB0,1 output delay time from SCK SB0,1 from SCK
tSIK4
100
ns
tKSI4
tKCY4/2
ns
tKSO4
RL = 1 k , CL = 100 pF*
VDD = 4.5 to 6.0 V
0 0
300 1000
ns ns
tKSB
tKCY4
ns
SCK from SB0, 1
tSBK
tKCY4
ns
SB0,1 low level width SB0,1 high level width
tSBL
tKCY4
ns
tSBH
tKCY4
ns
*
RL and CL are the SB0 and SB1 output line load resistance and load capacitance, respectively.
38
PD75P336 PD75P336 PD75304B
AC Timing Test Point(Exculuding X1 and XT1 Inputs)
0.8 VDD 0.2 VDD
Test Points
0.8 VDD 0.2 VDD
Clock Timings
1/fX tXL tXH
X1 Input
VDD -0.5 V 0.4 V
1/fXT tXTL tXTH
XT1 Input
VDD -0.5 V 0.4 V
TI0 Timing
1/fTI tTIL tTIH
TI0
39
PD75P336 PD75P336 PD75304B
Serial Transfer Timing 3-wired serial I/O mode:
tKCY1 tKL1 tKH1
SCK
tSIK1
tKSI1
SI tKSO1
Input Data
SO
Output Data
2-wired serial I/O mode:
tKCY2 tKL2 tKH2
SCK tSIK2
tKSI2
SB0,1
tKSO2
40
PD75P336 PD75P336 PD75304B
Serial Transfer Timing Bus release signal transfer:
tKCY3,4 tKH3,4
tKL3,4
SCK tSIK3,4
tKSB
tSBL
tSBH
tSBK
tKSI3,4
SB0,1 tKSO3,4
Command signal transfer:
tKL3,4 tKCY3,4 tKH3,4
SCK tSIK3,4
tKSB
tSBK
tKSI3,4
SB0,1 tKSO3,4
Interrupt Input Timing
tINTL
tINTH
INT0,1,2,4 KR0-7
RESET Input Timing
tRSL
RESET
41
PD75P336 PD75P336 PD75304B
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DAT RETENTION CHARACTERISTICS (Ta = -40 to 85 C)
PARAMETER Data retention supply voltage Data retention supply current*1 Release signal set time Oscillation stabilization wait time*2 SYMBOL VDDDR TEST CONDITIONS MIN. 2.0 TYP. MAX. 6.0 UNIT V
IDDDR
VDDDR = 2.0 V
0.1
10
A s
tSREL Release by RESET Release by interrupt request
0 217/fx *3
tWAIT
ms ms
*
1. Current flng in the built-in pull-up resistor is not included. 2. The oscillation stabilization wait time is the time CPU operation is stopped to prevent unstable operation at start of oscillation. 3. Depends on the basic interval timer mode register (BTM) setting (table below).
BTM3 -- -- -- --
BTM2 0 0 1 1
BTM1 0 1 0 1
BTM0 0 1 1 1
Waite Time (Figures in parentheses are for operation at fxx = 4.19 MHz) 220/fxx (approx. 250 ms) 217/fxx (approx. 31.3 ms) 215/fxx (approx. 7.82 ms) 213/fxx (approx. 1.95 ms)
42
PD75P336 PD75P336 PD75304B
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation HALT Mode STOP Mode Data Retention Mode Operating Mode
VDD VDDDR STOP Instruction Execution tSREL
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
HALT Mode STOP Mode Data Retention Mode Operating Mode
VDD VDDDR STOP Instruction Execution tSREL
Standby Release Signal (Interrupt Request) tWAIT
43
PD75P336 PD75P336 PD75304B
D/C PROGRAMING CHARACTERISTICS (Ta = 25 5 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V)
PARAMETER Input voltage high SYMBOL VIH1 VIH2 VIL1 VIL2 VL1 TEST CONDITION Except X1, X2 X1, X2 Except X1, X2 X1, X2 VIN = VIL or VIH IOH = -1 mA IOL = 1.6 mA MIN. 0.7VDD VDD -0.5 0 0 TYP. MAX. VDD VDD 0.3VDD 0.4 10 VDD -1.0 0.4 30 MD0 = VIL , MD1 = VIH 30 UNIT V V V V
Input voltage low Input leakage current Output voltage high Output voltage low VDD power supply current VPP power supply current
A
VOH VOL IDD IPP
V V mA mA
* 1. 2.
VPP must not exceed +13.5 V including overshoot. VDD should be applied before VPP and cut after VPP.
A/D PROGRAMING CHARACTERISTICS (Ta = 25 5 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V) (1/2)
PARAMETER Address setup time *2 (to MD0) MD1 setup time (to MD0) Data setup time (to MD0) Address hold time *2 (from MD0) Data hold time (from MD0) Data output float delay time from MD0 VPP setup time (to MD3) VDD setup time (to MD3) Initial program pulse width SYMBOL tAS *1 tAS TEST CONDITION MIN. 2 TYP. MAX. UNIT
s s
tMIS
tOES
2
tDS
tDS
2
s
tAH
tAH
2
s
tDH
tDH
2
s
tDF
tDF
0
130
s
tVPS
tVPS
2
s s
tVDS
tVCS
2
tPW
tPW
0.95
1.0
1.05
ms
* 1. Symbol of the corresponding PD27C256. 2. The internal address signal is incremented (+1) at the rising edge of the forth X1 input. The signal is not connected to pins.
44
PD75P336 PD75P336 PD75304B
A/D PROGRAMING CHARACTERISTICS (Ta = 25 5 C, VDD = 6.0 0.25 V, VPP = 12.5 0.3 V, VSS = 0 V) (2/2)
PARAMETER Additional program pulse width MD0 setup time (to MD1) Data output delay time from MD0 MD1 hold time (from MD0) MD1 recover time (from MD0) Program conuter reset time X1 input high/low width X1 input frequency
SYMBOL tOPW
*1 tOPW
TEST CONDITION
MIN. 0.95
TYP.
MAX. 21.0
UNIT
ms
tMOS
tCES
2
s
tDV
tDV
MD0 = MD1 = VIL
1
s
tM1H
tOEH tM1H + tM1R 50 s
2
s
tM1R
tOR
2
s
tPCR

10
s
tXH, tXL
0.125
s
fx

4.19
MHz
Initial mode set time MD3 setup time (to MD1) MD3 hold time (to MD1) MD3 setup time (to MD0 ) Data output delay time from address *2 Data output hold time from address *2 MD3 hold time (from MD0) Data output float delay time from MD3
tI
2 2
s s
tM3S

tM3H
2
s
tM3SR
Program memory read
2
s
tDAD
tACC
Program memory read Program memory read 0
2 130
s s s s
tHAD
tOH
tM3HR
Program memory read Program memory read
2 2
tDFR
*
1. Symbol of the corresponding PD27C256. 2. The internal address signal is incremented (+1) at the rising edge of the fourth X1 input. The signal is not connected to pins.
45
PD75P336 PD75P336 PD75304B
Program Memory Write Timing mode:
tVPS VPP VPP VDD VDD + 1 VDD VDD tVDS
tXH
X1
P40-P43 P50-P53 tI MD0 tPW MD1 tPCR MD2 tM3S tM1R tM0S Data Input tDS tOH
Data Output
tXL Data Input tDS tDH tAH tAS Data Input
tOPW
tM3H
MD3
Program Memory Read Timing mode:
tVPS VPP
VDD tVDS VDD + 1 VDD tXH
VDD
tXL tHAD P40-P43 P50-P53 tI MD0 tDV Data Output
tDAD Data Output
X1
VPP
tDFR tM3HR
tPCR MD2 tM3SR MD3
46
MD1
tM1S
tM1H
tDV
tDF

PD75P336
6. PACKAGE INFORMATION
5
80 PIN PLASTIC QFP ( 14)
A B
60 61
41 40 detail of lead end
D
C
S
80 1
21 20
F
G
H
IM
J K
P
N
L S80GC-65-3B9-3
NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q S
MILLIMETERS 17.2 0.4 14.0 0.2 14.0 0.2 17.2 0.4 0.8 0.8 0.30 0.10 0.13 0.65 (T.P.) 1.6 0.2 0.8 0.2 0.15+0.10 -0.05 0.10 2.7 0.1 0.1 3.0 MAX.
M
INCHES 0.677 0.016 0.551+0.009 -0.008 0.551+0.009 -0.008 0.677 0.016 0.031 0.031 0.012+0.004 -0.005 0.005 0.026 (T.P.) 0.063 0.008 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.106 0.004 0.004 0.119 MAX.
55
Q
47
PD75P336
80 PIN PLASTIC TQFP (FINE PITCH) (
A B
12)
60 61
41 40
detail of lead end
C
D
S Q
80
21 1 20
F
G
H
I
M
J
K
P
N L
NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS A B C D F G H I J K L M N P Q R S 14.00.2 12.00.2 12.00.2 14.00.2 1.25 1.25 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 INCHES 0.551 +0.009 -0.008 0.472 +0.009 -0.008 0.472 +0.009 -0.008 0.551 +0.009 -0.008 0.049 0.049 0.0090.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009
M
0.145 +0.055 0.0060.002 -0.045 0.10 1.05 0.050.05 55 1.27 MAX. 0.004 0.041 0.0020.002 55 0.050 MAX. P80GK-50-BE9-4
48
R
PD75P336
7. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the conditions in the table below. For detail of recommended soldering conditions, refer to the information document "Surface Mount Technology Manual" (IEI-1207). For soldering methods and conditions other than those recommended below, contact our salesman. Table 7-1 Soldering Conditions (1) PD75P336GC-3B9 : 80-pin plastic QFP ( 14mm)
Recommended Condition Symbol
5
Solderring Method
Solderring Conditions Solder bath temperature: 260 C. max., Duration: 10 sec. max., Number of times: Once, Time limit: 2 days* (thereafter 20 hours prebaking required at 125 C) Preheat temperature: 120 C max. (package surface temperature) Package Peak temperature: 230 C, Duration: 30 sec. max., (at 210 C or above), Number of times: Once, Time limit: 2 days* (thereafter 20 hours prebaking required at 125 C) Package Peak temperature: 215 C, Duration: 40 sec. max., (at 200 C or above), Number of times: Once, Time limit: 2 days* (thereafter 20 hours prebaking required at 125 C) Pin part temperature: 300 C or below, Duration: 3 sec. max. (per device side)
Wave soldering
WS60-202-1
Infrared reflow
IR30-202-1
VPS reflow
VP15-202-1
Pin part heating
(2) PD75P336GK-BE9 : 80-pin plastic TQFP (fine pitch) ( 12mm)
Recommended Condition Symbol
Solderring Method
Solderring Conditions Package Peak temperature: 235 C, Duration: 30 sec. max., (at 210 C or above), Number of times: Once, Time limit: 1 day* (thereafter 10 hours prebaking required at 125 C) Package Peak temperature: 215 C, Duration: 40 sec. max., (at 200 C or above), Number of times: Once, Time limit: 1 day* (thereafter 10 hours prebaking required at 125 C) Pin part temperature: 300 C or below, Duration: 3 sec. max. (per device side)
Infrared reflow
IR35-101-1
VPS reflow
VP15-101-1
Pin part heating
*
For the storage period after dry-pack decapsulation, storage conditions are max. 25 C, 65 % RH. Use of more than one soldering method should be avoided (except in the case of pin part heating).
Note
49
PD75P336 PD75P336 PD75304B PD75304B
APPENDIX A. LIST OF FUNCTIONS
Name Item CPU core ROM (bytes) RAM ( x 4 bits) General registers Main system clock Subsystem clock CMOS input CMOS input/output Input/ output ports CMOS output N-ch open-drain input/output LCD controller/driver 44 8 Internal pull-up resistor specifiable by software 20 8 Dual function as segment pins Same as at left (but no pull-up resistor) 8 (10 V, withstand voltage mask option pull-up capability)
PD75336
75X-High End 16256 (mask ROM) 768
PD75P336
PD75328
75X-Standard 8064 (mask ROM) 512 4 bits x 8 x 1 bank 0.95 s, 1.91 s, 15.3 s (at 4.19 MHz operation)
16256 (PROM)
4 bits x 8 x 4 banks 0.95 s, 1.91 s, 3.81 s, 15.3 s (at 4.19 MHz operation) 122 s (at 32.768 KHz operation)
Instruction cycle
8 (10 V withstand voltage, mask option pull-up capability)
Max.20 x 4 segment drive, variable duty: static, 1/2, 1/3, 1/4 * 8-bit resolution x 6-ch (successive approximation type) * Low-voltage operation capability: VDD = 3.5 to 6.0 V * Basic interval timer x 1 * Timer/event counter x 1 * Watch timer x 1
* A/D converter *
8-bit resolution x 8-ch (successive approximation type) Low-voltage operation capability: VDD = 2.7 to 6.0 V
Timer/counter
* Basic interval timer x 1 * Timer/event counter x 2 * Watch timer x 1 * NEC standard serial interface (SBI) * Clocked serial interface External: 3 Internal: 4 External: 1 Internal: 1
Serial Interface Vectored interrupt Test input Clock output (PCL) Buzzer output (BUZ)
External: 3 Internal: 3 External: 1 Internal: 1
, 524kHz, 262kHz, 65.5kHz (at 4.19MHz operation) 2kHz, 4kHz, 32kHz Transfer, addition/subtraction, increment/decrement, comparison VDD = 2.7 - 6.0 V 80-pin plastic QFP ( 14 mm) 80-pin plastic TQFP (fine pitch) ( 2kHz
8-bit data processing
Transfer
Operating voltage
5
Package On-chip PROM product
12mm) --
PD75P336
PD75P328
50
PD75P336 PD75P336 PD75P336 PD75304B PD75304B
APPENDIX B. DEVELOPMENT TOOLS
The following support tools are available for system development using the PD75P336. Language Processor
Host Machine
OS MS-DOSTM Ver. 3.30 to Ver. 5.00A* PC DOSTM (Ver. 3.1)
Supply Medium
Ordering Code (Product Name)
RA75X relocatable assembler
PC-9800 series
3.5-inch 2HD 5-inch 2HD
S5A13RA75X S5A10RA75X
IBM PC/ATTM
5-inch 2HC
S7B10RA75X
Remarks
Assembler operation is only guaranteed for the host machines and operating systems quoted above.
PROM Write Tools
PROM programmer which enables a single-chip microcomputer with on-chip PROM to be programmed in stand-alone mode or by operations from a host machine by connection of the supplied board and a separately available programmer adapter. Typical PROMs from 256K bits to 4M bits can also be programmed. PROM programmer adapter for the PD75P336GC, used connected to the PG-1500. PROM program adapter for the PD75P336GK, used connect to the PG-1500. Controls the PG-1500 on the host machine, with the PG-1500 and host machine connected via a serial or parallel interface.
Hardware
PG-1500
PA-75P328GC PA-75P336GK
Software
Host Machine PG-1500 controller PC-9800 series
OS MS-DOS Ver. 3.30 to Ver. 5.00A* PC DOS (Ver. 3.1)
Supply Medium
Ordering Code (Product Name)
3.5-inch 2HD
S5A13PG1500 S5A10PG1500 S7B10PG1500
5
5-inch 2HD
IBM PC/AT
5-inch 2HC
*
The task-swap function is provided with Ver.5.00/5.00A, but the function cannot be used with this software. PG-1500 controller operation is only guaranteed for the host machines and operating systems quoted above.
5
Remarks
51
PD75P336 PD75P336 PD75304B PD75304B
Debugging Tools
IE-75000-R*1
The IE-75000-R is an in-circuit emulator which corresponds to the 75X series. For PD75P336 development the IE-75000-R is used in conjunction with an emulation probe. Efficient debugging is possible by connection to a host machine and PROM programmer. Emulation board for the IE-75000-R and IE-75001-R. Incorporated in the IE-75000-R. Used in conjunction with the IE-75000-R or IE-75001-R to perform PD75P336 evaluation. The IE-75001-R is an in-circuit emulator which corresponds to 75X series. For PD75P336 development the IE-75001-R is used in conjunction with an emulation board IE-75000-R-EM*2 and emulation probe. Efficient debugging is possible by connection to a host machine and PROM programer. Emulation probe for PD75P336GC. Used connect with the IE-75000-R or IE-75001-R, IE-75000-REM. An 80-pin LCC socket (EV-9200GC-80) is also available to simplify connection to the user system. Emulation probe for PD75336GK. Used connected with the IE-75000-R or IE-75001-R, IE-75000-REM. An 80-pin conversion adapter (EV-9500GK-80 is also available to simplify connection to the user system. Connects the IE-75000-R or IE-75001-R to the host machine via by RS-232-C and contronix I/F and controls the IE-75000-R or IE-75001-R on the host machine.
IE-75000-R-EM
Hardware
IE-75001-R
EP-75338GC-R EV-9200G-80
EP-75336GK-R EV-9500GK-80
Host Machine Software
OS MS-DOS Ver. 3.30 to Ver. 5.00A*3
Supply Medium 3.5-inch 2HD
Ordering Code (Product Name)
IE control program
S5A13IE75X
PC-9800 series
5-inch 2HD
S5A10IE75X
IBM PC/AT
PC DOS (Ver. 3.1)
5-inch 2HC
S7B10IE75X
* 1. 2.
Maintenance product IE-75000-R-EM sold sparately The task-swap function is provided with Ver.5.00/5.00A, but the function cannot be used with this software. Operations of the IE control program is only guaranteed for the host machines and operating systems quoted above.
5
3.
Remarks
52
Development Tools Configuration 5
In-Circuit Emulator IE-75000-R IE-75001-R*1 RS-232-C
IE Control Program
Emulation Probe EP-75336GC-R EP-75336GK-R
Centronics I/F
IE-75000-R-EM
Host Machine PC-9800 Series IBM PC/AT (Symbolic Debugging Possible)
*2 User System
PG-1500 Controller
Pruducts Incorporating PROM PROM Programmer PG-1500
PD75P336GC PD75P336GK
Relocatable Assembler
+ Programmer Adapter PA-75P328GC PA-75P336GK
*
1. The IE-75001-R does not incorporate the IE-75000-R-EM (Available separately.) 2. EV-9200GC-80 EV-9500GK-80
PD75P336 PD75P336 PD75P336 PD75P336 PD75P336 PD75304B PD75304B
53
PD75P336 PD75P336 PD75304B PD75304B
54
PD75P336 PD75P336 PD75P336 PD75304B PD75304B
55
PD75P336
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment, Special : Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc.
M4 92.6
MS-DOSTM is a trademark of MicroSoft Corporation. PC DOSTM and PC/ATTM is a trademark of IBM Corporation.

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